On of the major results of the research within the PROMETHEUS project at the Department of Computer Engineering of Parma University is the development of the PAPRICA system, a low-cost massively parallel computer architecture, dedicated to the processing of images in real-time. PAPRICA system has been first simulated on a traditional serial architecture (SUN, PC), then on our Connection Machine CM-2 ( taking advantage of the similarity of their computational models) , and finally on April 1994 the Department of Electronics of the Politecnico di Torino gave birth to PAPRICA hardware board.
PAPRICA (PArallel PRocessor for Image Checking and Analysis) system, based on a hierarchical mathematical morphology computational model, has been designed as a specialized coprocessor to be attached to a general purpose traditional host ( PAPRICA front-end): in the current implementation it is integrated on a single VME board (6U) connected to a SPARC-based workstation. It comprises 5 major functional parts:
The first prototype of the PA is composed of an array of 4 x 4 full custom ICs (1.5 um CMOS, 45 mm2 , ~35000 transistors), each of them containing a sub- array of 4 x 4 Processing Elements (PE). In the present implementation, the PA is a 16 x 16 square matrix of 1-bit PEs each one with full 8-neighbors connectivity ; each PE has an internal memory composed of 64 bits only; data flow between the image memory and the PA through a 16-bit data bus. A block diagram of the complete system is presented in the following.
If you are interested in having more information, you may wish to load the following images or to contact directly the Page Manager:
Please do not hesitate to contact the Page Manager (Alberto Broggi) for any additional information on PAPRICA project, and on the algorithms developed on PAPRICA system.